The present invention relates generally to design tools for integrated circuits. More specifically, but without limitation thereto, the present invention relates to a method of placing control cells within a datapath macro to minimize signal propagation time and datapath macro area.
Integrated circuits typically include datapath macros. A datapath macro is an arrangement of datapath blocks connected by data buses and control signals. The data buses are generally routed vertically, and the control signals are generally routed horizontally. The datapath macro contains a set of datapath blocks placed along the vertical direction. Each datapath block has a datapath structure in which most data buses and control buses are located orthogonally with respect to each other and are connected to datapath cells in the datapath structure. Each of the datapath cells is connected to one or more of the data buses and to one or more of the control signals. As the size and complexity of the datapath macros and constituent datapath blocks increases, it becomes increasingly difficult for cell placement tools to arrange the datapath cells so that the signal propagation time through the datapath macro and the area of the datapath macro are minimized for datapath macro designs that include complex hierarchical structures, complex input constraints imposed on the placement of cells, pins, nets, gaps between cells, and so on. As the size and complexity of the datapath macros and constituent datapath blocks increases, therefore, signal propagation time through the datapath macro and the area of the datapath macro may be not be optimally minimized using conventional place and route methods.
The present invention advantageously addresses the problems above as well as other problems by providing a method of control cell placement in a datapath macro design that advantageously accommodates datapath structures having a large number of datapath and control cells, produces a globally ideal control cell placement in terms of connectivity length and interconnection delays.
In one embodiment, the present invention may be characterized as a method of control cell placement for an integrated circuit design that includes the steps of receiving as input a description of a datapath structure for a hardmac; calculating a globally optimum placement with respect to connection length and delay for a group of control cells in the plurality of control cells; placing the plurality of control cells in at least one placement box; adding the placement of the plurality of control cells to an existing placement of a plurality of datapath cells in the description of the datapath structure to generate a globally optimum datapath structure for the plurality of control cells; and generating as output the globally optimum datapath structure.
In another embodiment, the invention may be characterized as a computer program product that includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform the following functions: receiving as input a description of a datapath structure for a hardmac; calculating a globally optimum placement with respect to connection length and delay for a group of control cells in the plurality of control cells; placing the plurality of control cells in at least one placement box; adding the placement of the plurality of control cells to an existing placement of a plurality of datapath cells in the description of the datapath structure to generate a globally optimum datapath structure for the plurality of control cells; and generating as output the globally optimum datapath structure.